1. Field of the Invention
The present invention relates to a method for fabricating a power semiconductor device, and more particularly, to a method for fabricating a power semiconductor device having a trench gate structure
2. Description of the Related Art
Recently, power semiconductor devices having a trench gate structure have been widely used. Since the power semiconductor devices employ a trench gate structure, it is possible to prevent a junction field effect transistor (JFET) effect that may occur in a conventional planar structure and decrease the ON-resistance of the power semiconductor devices by decreasing the width of each cell and thus increasing the integration density of the power semiconductor devices. It is not difficult to manufacture a trench having a width of no greater than 1 μm in consideration of a current technological level. However, since the size of a source region and a body region is dependent on the size of openings for a source contact and a body contact, alignment margins approximately reach 2-5 μm in consideration of a current lithographic technology. In order to decrease the size of openings for a source contact and a body contact, various methods have been suggested.
FIGS. 1A through 1F are cross-sectional views illustrating a method for fabricating a power semiconductor device having a conventional trench gate structure. As shown in FIG. 1A, an n−-type epitaxial layer 102 is formed on an n+-type silicon substrate 100. A pad oxide layer 104, a nitride layer 106, and a low temperature oxide layer 108 are sequentially and thinly formed on the n−-type epitaxial layer 102. Next, as shown in FIG. 1B, the low temperature oxide layer 108, the nitride layer 106, the pad oxide layer 104, and the silicon substrate 100 are sequentially etched to a predetermined depth of the silicon substrate 100 using a predetermined mask layer pattern, for example, a photoresist layer pattern (not shown), to form a trench 110. Next, the photoresist layer pattern is removed. Next, as shown in FIG. 1C, a gate insulating layer 112 is formed along the surface of the trench 110, and a gate conductive layer 114 is formed to completely fill the trench 110. Next, as shown in FIG. 1D, the gate conductive layer 114 is etched back to be level with the top surface of the silicon wafer 100, and then an oxide layer 116 is formed on the gate conductive layer 114. Next, p-type impurity ions are implanted using the oxide layer 116 as an ion implantation mask to diffuse into the silicon wafer 100, thereby forming a p−-type body region 118. Next, n+-type impurity ions are implanted using a predetermined mask layer pattern (not shown) and the oxide layer 116 to diffuse into the silicon wafer 100, thereby forming an n+-type source region 120. Next, the mask layer pattern is removed. Next, as shown in FIG. 1E, spacer layers 122 are formed at the sidewalls of the oxide layer 116. P+-type impurity ions are implanted using the spacer layers 122 and the oxide layer 116 as ion implantation masks to diffuse into the silicon wafer 100, thereby forming a p+-type body contact region 124. Next, as shown in FIG. 1F, the top surfaces of the n+-type source region 120 and the p+-type body contact region 124 are exposed, and then a metal layer is deposited on the silicon wafer 100, thereby forming a source electrode 126. Next, a metal layer (not shown) is deposited at the bottom surface of the silicon substrate 100, thereby forming a drain electrode (not shown).
In the method for fabricating a power semiconductor device, since a source region and a body contact region are formed in a self-alignment manner, a smaller number of masks (five masks) are required in the manufacture of a power semiconductor device. In addition, according to the above method, it is possible to increase the integration density of cells and improve the current driving capability and ON-resistance characteristics of a power semiconductor device. However, as the size of cells of a power semiconductor devices decreases, the integration density of the cells continues to increase considerably. In addition, there is a limit in decreasing the width of cells due to restrictions on the width of the spacer layers 122 and the lengths of the n+-type source region 120 and the p+-type body contact region 124.